Researchers exhibit scaling of aligned carbon nanotube transistors to beneath sub-10 nm nodes


Researchers demonstrate the scaling of aligned carbon nanotube transistors to below sub-10 nm nodes
90 nm node carbon nanotube expertise. a, Carbon nanotube transistors based mostly on nanotube arrays with contacted gate pitch of 175 nm. b, Output traits of the carbon nanotube transistors with contacted gate pitch of 175 nm. c, False-color SEM picture of a consultant 6T-SRAM cell with a contacted gate pitch of 175 nm and an space of 0.976 μm2. Scale bar 200 nm. d, Benchmarking the ultrascaled A-CNT 6T-SRAM cell with silicon 130 nm, 90 nm and 45 nm expertise nodes for gate size, contacted gate pitch (CGP) and SRAM cell space. Credit score: Lin et al

Carbon nanotubes, massive cylindrical molecules composed of hybridized carbon atoms organized in a hexagonal construction, not too long ago attracted vital consideration amongst electronics engineers. As a consequence of their geometric configuration and advantageous digital properties, these distinctive molecules might be used to create smaller field-effect transistors (FETs) that exhibit excessive power efficiencies.

FETs based mostly on carbon nanotubes have the potential to outperform smaller transistors based mostly on silicon, but their benefit in real-world implementations has but to be conclusively demonstrated. A current paper by researchers at Peking College and different institutes in China, revealed in Nature Electronics, outlines the belief of FETs based mostly on carbon nanotubes that may be scaled to the identical measurement of a ten nm silicon expertise node.

“Current progress in attaining wafer-scale excessive density semiconducting carbon nanotube arrays brough us one step nearer to the sensible use of carbon nanotubes in CMOS circuits,” Zhiyong Zhang, one of many researchers who carried out the examine, informed “Nonetheless, earlier analysis efforts have primarily targeted on the scaling of channel or gate size of carbon nanotube transistors whereas retaining massive contact dimensions, which can’t be accepted for top density CMOS circuits in sensible functions.

“Our major goal of this work is to discover the true scaling functionality of carbon nanotube arrays utilizing two figures of advantage in silicon trade, that’s, contacted gate pitch and space of 6T SRAM cell, whereas sustaining the efficiency benefits.”

Zhang and his colleagues basically got down to exhibit the sensible worth of carbon nanotube transistors, displaying that they will outperform standard silicon-based FETs with a comparable gate pitch and a 6T SRAM cell space. To attain this, they first fabricated FETs based mostly on carbon nanotube arrays with a contacted gate pitch of 175 nm. This gate pitch was realized by scaling the gate size and get in touch with size to 85 nm and 80 nm, respectively.

“Remarkably, the transistors exhibited a formidable on-current of two.24 mA/μm and a peak transconductance of 1.64 mS/μm, surpassing the digital efficiency of silicon 45 nm node transistors,” Zhang mentioned. “As well as, 6T SRAM cell consisted of those ultra-scaled nanotube transistors has been fabricated inside 1 μm2, and capabilities appropriately. We then investigated the most important impediment, that’s, the contact resistance of carbon nanotube transistors for additional scaling.”

Researchers demonstrate the scaling of aligned carbon nanotube transistors to below sub-10 nm nodes
Sub-10 nm node carbon nanotube expertise. a, SEM and cross-sectional TEM photographs of an ultrascaled carbon nanotube transistor with a contacted gate pitch of 61 nm, a gate size (Lg) of 35 nm and a Lcon of 16 nm. Scale bar of the SEM picture: 200 nm; of the TEM picture: 100 nm. b, Comparability of Ion at numerous CGP for carbon nanotube FETs on this work with that for different reported aligned carbon nanotube FETs and silicon expertise. Credit score: Lin et al

Previous research have proven that when following a widespread contact scheme often called “aspect contact,” can solely be injected from the floor of carbon nanotubes. This makes the resistance of the nanotubes’ size dependent, limiting the extent to which they are often miniaturized.

To beat this situation, Zhang and his colleagues launched a brand new scheme that they confer with as “full contact.” This scheme entails slicing each ends of carbon nanotubes earlier than forming the contact, which in flip permits a part of the carriers to be injected from these ends.

“This new contact scheme permits carbon nanotube transistors to be additional downscaled to contacted gate pitch beneath 55 nm that corresponds to silicon 10 nm expertise node, whereas outperforming 10 nm node silicon transistors attributable to excessive provider mobility and Fermi velocity,” Zhang mentioned. “Our work experimentally demonstrated a real 90 nm node expertise utilizing carbon nanotubes, which might be made geometrically smaller and supply digital efficiency outperforming silicon 90 nm node transistors.”

This current paper introduces a dependable strategy to down-scale carbon nanotube transistors, with out compromising their efficiency. To this point, the crew used their technique to create a 90 nm node transistor, however by re-designing the construction of contacts they really feel these transistors might be shrunk beneath a sub-10 nm node.

Sooner or later, the work by Zhang and his colleagues may contribute to the creation of more and more smaller and environment friendly carbon nanotube-based transistors. This might have invaluable implications for the event of electronics.

“The subsequent problem that we are actually tackling is to scale down the contact geometry for carbon nanotube n-type transistors to setting up full CMOS expertise, which is the mandatory constructing blocks for contemporary digital ICs,” Zhang added.

“At present, we use scandium for the contact of n-type carbon nanotube transistors. Nonetheless, we face nice difficulties as we scale down the contact size as a result of oxidation of this low-work perform metallic. As well as, we’re working to precisely characterize the interface high quality between arrays and high-κ dielectric, bettering it to the extent of silicon CMOS transistors to boost gate controllability and reliability.”

Extra data:
Yanxia Lin et al, Scaling aligned carbon nanotube transistors to a sub-10 nm node, Nature Electronics (2023). DOI: 10.1038/s41928-023-00983-3

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Researchers exhibit scaling of aligned carbon nanotube transistors to beneath sub-10 nm nodes (2023, July 27)
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