Overcoming DDR challenges with DRAM AMI modeling

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With DDR stepping into the multi-gigabit vary, we see reminiscence methods adopting high-speed serial applied sciences. New reminiscence gadgets are utilizing equalization (e.g. DDR5) and/or multi-level modulations (e.g.  DDR6X and GDDR7 with PAM4). In consequence, designing with DDR turns into more difficult than ever earlier than and normal sign integrity evaluation is not enough.

As it is advisable regenerate your sign from a closed knowledge eye-diagram as a result of channel results, Keysight is providing a design movement, which helps you to:

  • Create and use JEDEC conform IBIS AMI fashions for DRAM drivers and receivers and simply join them to the reminiscence bus
  • Get full understanding of the channel traits by end-to-end simulations
  • Consider the design efficiency and margins of your DDR5 interface with IBIS-AMI modeling options resembling Choice Suggestions Equalization (DFE) and jitter monitoring